Modern integrated circuits (ICs) are easily damaged by excess voltages. Common sources of these potentially damaging voltages include electrical overstress (EOS) and electrostatic discharge (ESD). ESD, a serious issue in solid state electronics, is a transfer of electrostatic charge between bodies or surfaces at different electrostatic potentials either through direct contact or through an induced electrical field. ICs which are built using semiconductors, such as silicon, and insulating materials, such as silicon dioxide, can be permanently damaged when subjected to higher voltages that may be produced by ESD events.
Traditionally, on-chip circuits are employed to protect the IC during an ESD event. In conventional IC ESD protection schemes, special clamp circuits are often used to shunt ESD current between the IC power supply rails and thereby protect sensitive internal elements of the IC from damage. Such clamping circuits typically have a timer circuit (e.g., a resistor-capacitor (RC) timer, which may be referred to as a “transient detector”) and a large n-channel MOSFET device for discharging the high ESD current. Thus, a power rail clamp circuit is often employed within an IC so that if an ESD event is encountered on the IC's power rail, the clamp will turn on and reduce the voltage so that the IC's main devices (circuitry elements) will not get damaged. Implementations and use of such RC clamps are well-known in the art.
Exemplary ESD protection circuits include those described in U.S. Pat. No. 5,946,177 titled “Circuit for Electrostatic Discharge Protection”, U.S. Pat. No. 6,327,126 titled “Electrostatic Discharge Circuit”, U.S. Pat. No. 7,196,890 titled “Electrostatic Discharge Protection Power Rail Clamp with Feedback-Enhanced Triggering and Conditioning Circuitry”, U.S. Pat. No. 5,654,862 titled “Method and Apparatus for Coupling Multiple Independent On-Chip VDD Busses to ESD Core Clamp”, and Published U.S. Patent Application No. 2006/0250732 titled “Transient Pulse, Substrate-Triggered BICMOS Rail Clamp For ESD Abatement.”
A given integrated circuit (IC) package may have multiple die implemented therein. Traditionally, there are on-chip ESD protection circuits which are integrated into the input/output (I/O) circuits to protect a given die during an ESD discharge event. These circuits provide the required protection for that particular die. Thus, in traditional ESD protection schemes for IC packages including multiple die, an ESD protection circuit may be implemented within each die for protecting its particular die against excess voltage events (e.g., ESD events) that arise within the particular die. As an example, an ESD protection circuit may have a pair of back-to-back diodes that are arranged within a given die for providing a discharge path for excess voltage events that arise within the given die. Similarly, another pair of back-to-back diodes may be arranged within another die for providing a discharge path for excess voltage events that arise within such other die. Such utilization of back-to-back diodes for providing an excess voltage discharge path is well-known in the art. In general, such diodes are usually reverse-biased (non-conducting) under normal operating conditions, but upon an excess voltage event (e.g., ESD) occurring which causes an excess charge on one side of the diode pair exceeding some threshold amount, a diode in the pair becomes forward-biased (conducting) so as to provide a discharge path for the excess voltage.
In a package that has multiple die, the I/O signals of one die may communicate with I/O signals of one or more other die in the same package. Different die in the package may have different levels of sensitivity to noise. For instance, these die in a given package may contain completely digital circuits or RF/analog circuits, which are highly sensitive to substrate noise and cross talk. Typically, if a die contains circuitry that is highly sensitive to noise (e.g., sensitive RF/analog circuits), it requires proper isolation from the substrate noise which may be introduced by another die, such as by a digital die in the package.
ESD protection for an overall package containing multiple die becomes more challenging due to such problems as noise isolation, cross talk, etc. Moreover, the communication between multiple die and the signals which interface between different power domains adds to the ESD vulnerability of the package.